1. Field of the Invention
The present invention relates to ESD protection devices for protecting semiconductor ICs and other electronic components against static electricity, and more specifically, to a chip size package (CSP-type) ESD protection device including a functional portion provided on a silicon substrate.
2. Description of the Related Art
Various electric apparatuses, such as mobile communication terminals, digital cameras, and notebook PCs include semiconductor integrated circuits (IC chips) which define logic circuits, memory circuits, and other circuits. Such semiconductor integrated circuits are constant-voltage driving circuits that include fine wiring patterns which are provided on a semiconductor substrate, and are therefore vulnerable to an electrostatic discharge, such as a surge. Such semiconductor integrated circuits are protected against electrostatic discharges using ESD (Electro-Static-Discharge) protection devices.
As described in Japanese Unexamined Patent Application Publication No. 4-146660, Japanese Unexamined Patent Application Publication No. 2001-244418, Japanese Unexamined Patent Application Publication No. 2007-013031, and Japanese Unexamined Patent Application Publication No. 2004-158758, ESD protection devices including ESD protection circuits that include diodes that are provided in semiconductor substrates are widely used. The protection provided by a diode in an ESD protection circuit is achieved by utilizing a breakdown phenomenon that occurs at the time when a reverse direction voltage is applied to the diode, and the breakdown voltage functions as an operating voltage.
Japanese Unexamined Patent Application Publication No. 2004-158758 discloses an example of a semiconductor device including a rewiring line used to form an ESD protection device as a surface mount device. Here, a configuration of the ESD protection device disclosed in Japanese Unexamined Patent Application Publication No. 2004-158758 will be described with reference to FIG. 1. FIG. 1 is a cross-sectional view of a semiconductor device that defines the ESD protection device disclosed in Japanese Unexamined Patent Application Publication No. 2004-158758. The semiconductor device includes a silicon substrate (semiconductor substrate) 1. An integrated circuit is disposed in a center portion on the top surface of the silicon substrate 1, and a plurality of connection pads 2 connected to the integrated circuit are disposed in a periphery on the top surface. An insulating film 3 made of silicon oxide is disposed on the top surface of the silicon substrate 1, except for center portions of the connection pads 2. The center portions of the connection pads 2 are exposed through openings 4 provided in the insulating film 3.
A protective film (insulating film) 5 made of organic resin, such as polyimide, is disposed on the top surface of the insulating film 3. The protective film 5 includes openings 6 in portions thereof corresponding to the openings 4 in the insulating film 3. The protective film 5 includes recessed portions 7 disposed in a rewiring forming region on the top surface thereof. The recessed portions 7 communicate with the openings 6.
A rewiring line 8 including an underlying metal layer 8a and an upper metal layer 8b disposed on top of the underlying metal layer 8a is arranged so as to extend from the top surfaces of the connection pads 2 exposed through the openings 4 and 6 to predetermined portions on the top surface in the recessed portions 7 in the protective film 5.
Pillar-shaped electrodes 10 are disposed on the top surfaces of connection pad portions in the rewiring line 8. A sealing film 11 is disposed on the top surface of the protective film 5, which includes the rewiring line 8, so that the top surface of the sealing film 11 is flush with the top surfaces of the pillar-shaped electrodes 10. Solder balls 12 are disposed on the top surfaces of the pillar-shaped electrodes 10.
Meanwhile, if the above-described ESD protection device is disposed in a high-frequency circuit, a problem occurs in that high-frequency signals are affected by the parasitic capacitance of the diode. That is, the insertion of an ESD protection device into a signal line may cause impedance variations due to the parasitic capacitance of the diode, which results in signal loss.